(1) Field of the Invention
The invention relates to an integrated circuit device and, more particularly, to a device for protecting an integrated circuit from electrostatic discharge.
(2) Description of the Prior Art
Designing electrostatic discharge (ESD) protection structures for high-speed analog or radio frequency (RF) applications presents many challenges. These challenges are due to the stringent requirements for low input impedance and to the need to keep the area of the input protection devices to a minimum. Referring now to FIG. 1, a prior art ESD protection circuit is shown. In this traditional approach, a grounded gate NMOS (GGNMOS) device 10 is used. The gate of the device is connected to the grounded pin or pad 18. During an ESD event on the input pin 14, the parasitic bipolar device formed by the source, bulk, and drain (n-p-n) conducts current away from the input pin 14 to the ground pin 18 due to reverse junction breakdown and secondary breakdown. The traditional GGNMOS device 10 has proven quite useful over the years. However, the device 10 must be made quite large to dissipate the ESD energy without device failure. It is found that the GGNMOS device 10 adds too much parasitic capacitance to the input pin 14. This, in turn, degrades the analog performance of the pin 14. In addition, it is found that the secondary breakdown, or snap-back, performance of the GGNMOS device 10 is degraded in state of the art CMOS technologies. Due to this degradation, the device 10 must be made even larger to accommodate the ESD energy. Again, the capacitance of the device increases due to the increase in the drain area coupled to the pin 14.
Referring now to FIG. 2, various techniques have been proposed to improve the turn-ON characteristics of the NMOS protection device 22. One such approach is called gate coupling. In a gate coupled NMOS (GCNMOS) device 22, the gate is not connected to ground directly. Rather, the gate is coupled to a control circuit 26 and 30. In this example, the gate of the NMOS is coupled to a RC network comprising a capacitor C 26 and a resistor R 30. During normal operation, the gate is discharged to the ground pin 38 through R 30. During the ESD event, the capacitor C 26 couples a larger voltage onto the gate than would occur without the capacitor. This gate coupling improves the turn-ON characteristic of the device 22. However, the capacitor C 26 and resistor R 30 network increases the area of the device.
Referring now to FIG. 3, a second prior art approach to improving the performance of the NMOS device 42 is shown. In this case, the bulk, or substrate, of the device 42 is biased using a substrate bias generator 54. The substrate bias generating circuit 54 also improves the turn-ON characteristic of the NMOS device 42, but this improvement requires substantial area and increases the capacitance at the input node 46.
Several prior art inventions relate to PIN diode devices and to ESD. U.S. Pat. No. 6,259,134 B1 to Amarantunga et al describes an MOS-controllable, power semiconductor trench device. The device comprises a PIN diode in parallel with a thyristor. U.S. Application 2002/0066929 A1 to Voldman discloses an ESD power clamping circuit comprising a FET and a bipolar element. In one embodiment, a diode, or a series of diodes, is coupled to the gate of the FET. The diode may comprise a PIN diode. U.S. Application 2002/0088978 A1 to Trainor et al shows an active matrix device where a pair of opposing, lateral PIN diodes is used to provide ESD protection across the row and column lines.